Semiconductor memory including address multiplexing circuitry for changing the order of supplying row and column addresses between read and write cycles

ABSTRACT

A memory system includes a semiconductor memory device having random-access memory cells arranged as an integrated memory cell array, a plurality of bit lines for exchanging data with each of the memory cells, and a plurality of word lines intersecting with the bit lines. The semiconductor memory device is an address multiplexed type device in which a column address for selecting a bit line and a row address for selecting a word line are obtained from a single circuit. In this device, the input order of the column and row addresses during a read cycle differs from that during a write cycle.

This application is a continuation of application Ser. No. 07/274,483,filed on Nov. 22, 1988, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and, moreparticularly, to a method of accessing a dynamic Random Access Memory(dRAM) in which dynamic memory cells for individual cell access areintegrated, and a dRAM system.

2. Description of the Related Art

A conventional semiconductor memory device is generally operated inresponse to a control signal from an external Central Processing Unit(CPU). In the dRAM, an upper address designation signal, a lower addressdesignation signal, row address strobe RAS, column address strobe CAS,write trigger signal WE, and the like are used. These control signalsmust be input from the external CPU or the like at a voltage, an order,and a timing which are prescribed by specifications of the semiconductormemory device so as to properly operate the semiconductor memory device.

The row address strobe (to be referred to as an RAS hereinafter) is asignal for selecting a mode which designates a row of the semiconductormemory device, and a column address strobe (to be referred to as a CAShereinafter) is a signal for selecting a mode which designates a columnof the semiconductor memory device. In both the read and write modes,signals RAS and CAS are always input in the order named.

SUMMARY OF THE INVENTION

A method of accessing a dRAM according to the present invention ischaracterized in that in a dRAM of an address multiplex system, theorder of input of column and row addresses during a read cycle differsfrom that during a write cycle.

A dRAM system of the address multiplex type according to the presentinvention is characterized by comprising an address data selector fordividing the row and column addresses from a CPU into upper and loweraddresses and time-divisionally supplying them to a dRAM chip, and agate circuit for designating to the selector which of the upper andlower addresses is to be input first, in response to an external controlsignal.

According to the method of accessing the dRAM of the present invention,e.g., an arrangement in which a latch-type memory cell is arrangedbetween a bit line and an input/output line is utilized. Thus, during aread cycle, RAS goes from "1" to "0" prior to CAS. During a write cycle,on the other hand, CAS goes from "1" to "0" prior to RAS. Therefore, nolimitation is imposed on the timings of enabling the word line and CSL(column select line) in the write mode, thus ensuring a high-speed writeoperation of the dRAM and an easy designing thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an arrangement of a main part of adRAM according to an embodiment of the present invention;

FIGS. 2A, 2B, 2C, and 2D, are timing charts for explaining read andwrite operations performed by the embodiment shown in FIG. 1;

FIG. 3 is a diagram showing in detail an arrangement of the circuitshown in FIG. 1;

FIG. 4 is a diagram showing an arrangement of a control circuit of adRAM chip shown in the arrangement of FIG. 1;

FIGS. 5A to 5W are timing charts for explaining operations performed bythe embodiment in FIG. 3 during a read cycle;

FIGS. 6A to 6Y are timing charts for explaining operations performed bythe embodiment in FIG. 3 during a write cycle;

FIG. 7 is a circuit diagram showing an arrangement of a column selectline decoder;

FIGS. 8A and 8B are a circuit diagram and timing chart for explaining anexample of a driving operation of the word lines; and

FIG. 9 is a circuit diagram showing a modification of a second transfergate used in the embodiment in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will now be described below, withreference to the accompanying drawings.

FIG. 1 shows an arrangement of a main part of a dRAM according to anembodiment. A plurality of pairs of bit lines BLi and BLi (i=1, 2, 3, .. .) and a plurality of word lines MWn (n=1, 2, 3, . . .) are formedsuch that they intersect each other on a semiconductor substrate, withdRAM cells MCn (n=1, 2, 3, . . .) being arranged at the respectiveintersecting points. Each of dRAM cells MCn is selected and driven by acorresponding one of word lines MW, and data is exchanged between bitlines BL and BL. Besides dRAM cells, each of bit line pairs BL and BLincludes dummy cells DC1 and DC2 which are driven by dummy word linesDW1 and DW2, respectively. Bit line sense amplifiers 10 (10-1, 10-2, . ..) for detecting the data read out at bit lines BL and BL are arrangedat one ends of bit lines BL and BL. Reference numerals 50 (50-1, 50-2, .. .) denote circuits (to hereinafter be referred to precharge circuits)for equalizing and precharging bit lines BL and BL. Latch-type memorycells 20 (20-1, 20-2, . . .) are connected to the other ends of bitlines BL and BL via first transfer gates 30 (30-1, 30-2, . . .).Latch-type memory cells 20 are connected to input/output lines I/O andI/O via second transfer gates 40 (40-1, 40-2, . . .).

FIGS. 2A, 2B, 2C, and 2D are timing charts for explaining operations inthe arrangement shown in FIG. 1. In a read mode, the signals RAS and CASare input in the order shown in FIGS. 2A and 2B, as control signals tothe inner units of the dRAM from an external CPU or the like. When RASis enabled, word line MW is also enabled. Then, the voltage of bit lineBL is detected by the sense amplifier and the logic level ("1" or "0")is determined. Bit line BL is kept at the detected logic level and wordline MW is disabled. On the other hand, by enabling CAS, CSL is enabledand a given column is designated. Then, readout of the data is started.At this time, in order to smoothly read out the data, a certainrelationship between the input timings of the signals must be kept. Inother words, signal CSL for selecting a column line must be enabledafter initialization of sense amplifiers SA is completed. Thisrelationship between the input timings may be same as that in theconventional dRAM.

When the conventional dRAM is in the write mode, signals RAS and CAS areinput from the external CPU or the like in the order stated, i.e. thesame as in the case of the read mode, word line MW is enabled inresponse to RAS, and the voltage of bit line BL is detected by the senseamplifier. The detected logic level is determined and bit line BL iskept at the detected logic level. On the other hand, CAS is enabled inresponse to a signal from the external CPU or the like and thereafterCSL is enabled, thus selecting and determining the column line. At thistime, in order to write the data correctly, word line MW must bedisabled after the above-described sense amplifier is initialized. Ifthis order is reversed, a normal write operation cannot be performed.

When RAS is enabled before CAS, however, time t RCD (i.e., periodbetween the enabling of RAS and that of CAS) will become longer in thecase where a latch-type memory cell is connected between each bit lineand each input/output line, thereby to precharge the bit line while RASis active. If time t RCD becomes longer, word line MW will be madeinactive before CSL is enabled. Consequently, the timing of generatingRAS and CAS is limited.

On the other hand, when the gating is performed such that word line MWis made inactive after CSL has been enabled, an ample gating margin isrequired, inevitably making it difficult to ensure a high-speed datawrite operation. Further, when the gating is performed in such a way, itis necessary to delay the rising of RAS by the same period as theenabling of word line MW has been delayed.

According to the present invention, the input order of RAS and CAS inthe write mode of the conventional dRAM is reversed to that in the readmode, thereby preventing abnormal write operations due to the reversedorder of active periods of the sense amplifiers and CSL. Therefore, thetimings of RAS and CAS can be freely set, thus realizing a stableoperation in the write mode.

FIG. 3 shows a detailed arrangement of the dRAM in FIG. 1. In FIG. 3,dRAM cells and dummy cells MC and DC are of well known type whichinclude MOS transistors and capacitors, respectively. The referencevoltage terminal of each capacitor is connected to plate power supplyVPL. Dummy cells DC1 and DC2 include n-channel MOS transistors Q9 andQ10, respectively. Bit line sense amplifier 10 comprises a flip-flopincluding n-channel MOS transistor pair (Q4 and Q5), and a flip-flopincluding p-channel MOS transistor pair (Q6 and Q7). Enable signals φseand φse are input to the common sources of the respective pairs.Precharge circuit 50 comprises three n-channel MOS transistors Q1 to Q3each gate of which commonly receives equalize signal EQL1. Referencenumerals Q1 and Q2 denote precharge transistors. The sources oftransistors Q1 and Q2 are respectively connected to bit lines BL and BL,and the drains of them are commonly connected to precharge power supplyVBL. Reference numeral Q3 denotes the MOS transistor for equalizing thebit lines, its source and drain being respectively connected to bitlines BL and BL.

Latch-type memory cell 20 comprises a flip-flop including n-channel MOStransistor pair (Q18 and Q19), and a flip-flop including p-channel MOStransistor pair (Q21 and Q22). The sources of each transistor pairreceive latch clocks φCE and φCE. Reference numeral Q20 denotes ann-channel MOS transistor for equalizing. Nodes A and A of such alatch-type memory cell 20 are respectively connected to bit lines BL andBL through n-channel MOS transistors Q16 and Q17 included in firsttransfer gate 30. These nodes A and A are also connected to input/outputlines I/O and I/O through n-channel MOS transistors Q23 and Q24 includedin second transfer gate 40, respectively. First transfer gate 30 iscontrolled by clock φT. Second transfer gate 40 is connected to columnselect line CSL selected by a column address.

FIG. 4 shows an arrangement of an external control circuit outside thedRAM chip, for differentiating an input order of row and columnaddresses during a read cycle from that during a write cycle in the dRAMof the above embodiment. Address data selector 70 for addressmultiplexing is arranged between dRAM chip 60 and CPU 80. This addressdata selector 70 multiplexes input row and column addresses so that theupper n bits may be defined as a column address, and the lower n bitsmay be defined as a row address. Then, the multiplexed addresses aresupplied to address terminals of dRAM chip 60. Address selector 70includes a select control terminal SELECT for selecting an address whichof the lower column and upper row addresses is to be output first. Gatecircuit 90 is arranged to supply "0" or "1" to the control terminalSELECT in correspondence with a combination of RAS, CAS, and triggersignal WE. At first, all of RAS, CAS, and WE are set at level "1". WhenRAS is set at level "0", control signal "1" is output to the controlterminal SELECT from gate circuit 90, and a row address is output fromaddress data selector 70 prior to a column address. After that, when CASis set at "0", the control signal goes "0" and column address is output.These operations are during the read cycle. During the write cycle, CASand WE go "0" prior to RAS, and the column address is output prior tothe row address in response to control signal "0" from gate circuit 90.Subsequently, when RAS goes "0", the control signal is set at "1",thereby outputting the row address.

Note that, in FIG. 4, delay circuits D1 and D2 are arranged at inputterminal sections of RAS and CAS so as to provide a set-up time to aninput address of dRAM chip 60.

An operation during the read cycle of the dRAM having the abovearrangement will be described below with reference to FIGS. 5A to 5W.FIGS. 5A to 5N show signal waveforms when data of the latch-type memorycell is transferred to the input/output line while performing a bit-lineprecharge in the system for precharging the bit line to be (1/2) V_(DD).At first, the level of bit line equalize signal EQL1 (FIG. 5M) is set atV_(DD), and the level of bit line precharge power supply VBL (not shown)is set at (1/2) V_(DD). Therefore, bit lines BL and BL (FIGS. 5P and 5Q)are all precharged to be (1/2) V_(DD). Assume that, in ith bit line pair(BLi and BLi), V_(DD) (logic "1") is written in node N1 (FIG. 5V) of acapacitor of dRAM cell MC1. Also assume that node N3 of a capacitor ofdummy cell DC2 (FIG. 5W) is initialized at the level of (1/2) V_(DD) bywrite power supply VDC.

When clock RAS (FIG. 5A) is set at logic "0" (VIL) from logic "1" (VIH)and is enabled, equalize signal EQL1 (FIG. 5M) is decreased from V_(DD)to V_(SS) and bit lines BL and BL are disconnected from each other. Inaddition, EQL2 (FIG. 5N) is also decreased from V_(DD) to V_(SS) and thememory node of the dummy cell is set in a floating state. For example,if word line MW1 (FIG. 5E) is selected and the level thereof and thelevel of dummy word line DW2 (FIG. 5F) are increased from V_(SS) to(3/2) V_(DD) the contents of dRAM cell MC1 and dummy cell DC2 are readout at bit lines BL and BL (FIGS. 5P and 5Q), respectively. Note thatequalize signal EQL3 (FIG. 5O) of latch-type memory cell 20 is decreasedfrom V_(DD) to V_(SS) just before this reading. Subsequently, n-channelsense enable signal φSE (FIG. 5I) decreases from the 1/2 V_(DD) level tothe V_(SS) level, and p-channel sense enable signal φSE (FIG. 5H) alsorises from the 1/2 V_(DD) level to the V_(DD) level. Therefore, bit lineBL (FIG. 5P) at the side where the data of logic "1" is read out isincreased to V_(DD), and bit line BL (FIG. 5Q) in which the data ofdummy cell DC2 is read out is decreased to V_(SS).

Clock φT (FIG. 5J) changes from V_(SS) to V_(DD), and first transfergate 30 is turned on. When the latch signals φCE and φCE (FIGS. 5K and5L) change from (1/2) V_(DD) to V_(DD) and V_(SS), respectively, thecontents of bit lines BL and BL (FIGS. 5P and 5Q) are transferred tonodes A and A (FIGS. 5R and 5S) respectively of the latch-type memorycell 20. Thus, if external write trigger signal WE (not shown) outsidethe dRAM chip is set at logic "1" in the read mode when the data of BLand BL are transferred to latch-type memory cell 20, bit line prechargeis automatically started. The operation will be described hereinafter indetail.

After the selected and readout memory cell MC1 is sufficiently restored(i.e., rewritten or refreshed), select and dummy word lines MW1 (FIG.5E) and DW2 (FIG. 5F) are decreased from (3/2) V_(DD) to V_(SS), andthese lines are not selected. After that, clock φT (FIG. 5J) isdecreased from V_(DD) to V_(SS), and latch-type memory cell 20 isdisconnected from bit lines BL and BL. Bit line equalize signal EQL1(FIG. 5M) is increased from V_(SS) to V_(DD), and precharge circuit 50is operated, thus precharging the bit lines. At this time, CAS clock(FIG. 5B) goes from logic "1" to logic "0". Therefore, if, e.g., an ithcolumn is selected, the level of column select line CSLi (FIG. 5G) isincreased from V_(SS) to V_(DD) or to a boosted voltage of (3/2) V_(DD).Second transfer gate 40 is turned on and nodes A and A (FIGS. 5R and 5S)of latch-type memory cell 20 are connected to input/output lines I/O andI/O respectively. In this case, I/O (FIG. 5T) is kept at level V_(DD),and I/O (FIG. 5U) is decreased from V_(DD) to V_(SS), and outputterminal DOUT outputs logic "1".

According to the embodiment as described above, by arranging thelatch-type memory cells at the bit lines and temporarily storing thereadout data therein, the bit lines can be precharged when RAS isenabled.

FIGS. 6A to 6Y show signal waveforms for explaining an operation duringthe write cycle. During the write cycle, CAS (FIG. 6B) goes from "1" to"0" (active) prior to RAS (FIG. 6A). At the same time, write triggersignal WE (FIG. 6C) goes to "0" (active). Therefore, a column address isinput to the dRAM chip prior to a row address. If, e.g., an ith columnis selected, column select line CSLi (FIG. 6I) is not enabled at thistime. However, the column address is latched by a column decoder forselecting the column select line.

FIG. 7 shows a main part of the column decoder. When CAS goes "0" priorto RAS, and RAS goes "0", AND gate 100 is enabled since the first andsecond inputs of AND gate 100 are both "1". Column address Aci is inputto the dRAM chip, and output from a column address buffer. Output Aci issupplied to AND gate 100 as the third input. Since AND gate 100 isenabled, Aci is output through an inverter as CSLi.

A write system circuit (not shown) is operated and a data-in buffer isthen operated, thus enabling the sense amplifiers of input/output linesI/O and I/O. For example, if input data is set at "0", in this case, I/O(FIG. 6V) is decreased from V_(DD) to V_(SS), and I/O (FIG. 6W) is keptat V_(DD).

When RAS goes from "1" to "0" after WE and CAS respectively go from "1"to "0" (FIGS. 6A to 6C), equalize signal EQL1 to EQL3 (FIGS. 6O and 6Q)are decreased from V_(DD) to V_(SS), and bit lines BLi and BLi (FIGS. 6Rand 6S) and nodes Ai and Ai (FIGS. 6T and 6U) of latch-type memory cellsare set at 1/2 V_(DD) level, in a floating state. The levels of wordline MW1 (FIG. 6G) and dummy word line DW2 (FIG. 6H) are increased fromV_(SS) to (3/2) V_(DD) in response to the input row address (FIG. 6D).At the same time, column select line CSLi (FIG. 6I) is increased fromV_(SS) to V_(DD) in response to column address Aci which was alreadyinput to the column decoder (AND gate 100 in FIG. 7), and clock φT (FIG.6L) is also increased from V_(SS) to V_(DD). Therefore, first and secondtransfer gates 30 and 40 are turned on, and bit lines BLi and BLiconnected to input/output lines I/O and I/O, respectively.

Subsequently, n-channel sense amplifier enable signal φSE (FIG. 6K) andmemory cell latch signal φCE (FIG. 6N) are simultaneously decreased from(1/2) V_(DD) to V_(SS). P-channel sense amplifier enable signal φSE(FIG. 6J) and memory cell latch signal φCE (FIG. 6M) are simultaneouslyincreased from (1/2) V_(DD) to V_(DD), and the data is written in theselected memory cell and nonselected memory cells connected to word lineMN are restored. More specifically, since node N1 of the selected dRAMcell MC1 and node N2 of dummy cell DC2 are respectively connected to bitlines BLi and BLi, node N1 (FIG. 6X) is decreased from V_(DD) to V_(SS)and logic "0" is written in dRAM cell Mcl of bit line BLi. Therefore,node N3 (FIG. 6R) is increased from (1/2) V_(DD) to V_(DD). After thenon-selected memory cell is sufficiently restored (refreshed), word lineMW1 (FIG. 6G) and dummy word line DW2 (FIG. 6H) are decreased from (3/2)V_(DD) to V_(SS), these lines are not selected. At substantially thesame time, clock φT (FIG. 6L) is decreased from V_(DD) to V_(SS), andlatch-type memory cell 20 is disconnected from bit lines BL and BL.Therefore, bit line equalize signal EQL1 (FIG. 6O) is increased fromV_(SS) to V_(DD), precharge of the bit lines is started. At the sametime, equalize signal EQL2 (FIG. 6P) is increased from V_(SS) to V_(DD),and an initialization level of (1/2) V_(DD) is written in dummy cellsDC1 and DC2.

When write trigger signal, WE (FIG. 6C) returns from "0" to "1", theoperation of the write system circuit is stopped and the operation ofthe read system circuit is started. Data of ith latch-type memory cell20 is output from a data-out buffer (not shown). In this case, sincelogic level "0" is written, "0" is output.

When CAS (FIG. 6B) goes from "0" to "1", the data-out buffer andinput/output lines are reset. However, latch-type memory cell 20 is notreset.

When RAS (FIG. 6A) finally returns from "0" to "1", equalize signal EQL3(FIG. 6Q) is increased to V_(DD), thus resetting latch-type memory cell.

FIGS. 8A and 8B respectively show a word line driving circuit and itsoperation timing. During period τ1 after RAS goes from "1" to "0", wordline MW is enabled. Word line MW is kept at logic "1" only during periodτ2 and is then automatically disabled.

According to the embodiment shown in FIGS. 3 and 4, by arranginglatch-type memory cell 20 for each bit line pair (BL and BL), the bitline can be precharged when RAS is enabled. A column select line isselected in response to CAS and sense data is externally output, so thatthe data is readout. During the write cycle, CAS is input prior to RASand the write circuit system is operated to receive the data ininput/output lines I/O and I/O. The bit line sense amplifier is operatedin response to RAS, and the data is written and the nonselected line isrestored. After that, the bit line can be precharged when RAS isenabled, in the same manner as during the read cycle.

The effect of the present invention as described above is as follows. Inthis embodiment, during the write cycle, since CAS is input prior toRAS, a sufficient time margin can be obtained until a word line isturned off after column select line CSL is enabled. Therefore, as duringthe read cycle, the cycle time is substantially determined in responseto RAS during the write cycle. Hence, the timing of enabling RAS is notinfluenced by the timing of enabling CAS, thus ensuring a high-speedwrite operation of the dRAM and an easy designing thereof.

When write trigger signal WE returns from "0" to "1", CAS is toggledwhile RAS is at level "0" and a column address is input. Then, the dataof latch-type memory cell can be readout at random. Even if the columnaddress is not input and only CAS toggles, the data can be seriallyreadout.

The present invention is not limited to the above embodiment. Forexample, as shown in FIG. 9, n-channel MOS transistors Q25 and Q26 maybe added to second transfer gate 40 in the above embodiment, and thegates of these transistors may be driven in response to clock φW whichis enabled at substantially the same time as the word line is selectedduring both the read and write cycles. Thus, during the write cycle inwhich CAS is set at "0" prior to RAS, as soon as the column address isinput to the dRAM chip, the selected column select line CSL can beincreased from V_(SS) to V_(DD) or (3/2) V_(DD).

According to the embodiment shown in FIG. 1, latch-type memory cells arearranged at respective bit lines and an address input order during thewrite cycle is reversed to that during the read cycle. Therefore, thecycle time can be shortened. In the conventional dRAM arrangementwithout such a latch-type memory cell, the input order of the row andcolumn addresses during the write cycle can be differentiated from thatduring the read cycle.

Various changes and modifications of the present invention may beeffected without departing from the spirit or scope of the invention asdefined in the appended claims.

What is claimed is:
 1. A memory system comprising:a memory means formemorizing data, having a plurality of terminals for receiving addressdata, and receiving row and column address data through said terminals;an address data selector means for receiving said row and column addressdata at the same time, and supplying one of said row address data andsaid column address data to said terminals of said memory means, andthen supplying the other of said row address data and column addressdata to said terminals; a logic circuit means for receiving a rowaddress strobe signal and a column address strobe signal, and foroutputting a signal indicative of a selection order of said row addressdata and said column address data to said address data selector meansbased on a timing sequence of said row address strobe signal and saidcolumn address strobe signal; and wherein said address data selectormeans and said logic circuit means change the order of supplying saidcolumn address data and said row address data between a read cycle and awrite cycle.
 2. A system according to claim 1, wherein said memory meansfurther comprises:a plurality of memory cells for storing data; aplurality of pair of bit lines connected to said memory cells through aplurality of switching transistors; a plurality of word lines connectedto gates of the switching transistors respectively; and means to makeone of said word lines active and then inactive during an active periodof said row address strobe signal.